Submission Open for 2024 |
Last Date of Submission : |
20th, March-2024 |
Acceptance Notification : |
After the Peer Review |
Last Date of Publication : |
30th, March-2024 |
Volume13 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
S.NO | TITLE | PAGE NO | DOWNLOAD | |
IJSETR 2056 | Enhanced Web Security using Multi Level Authentication Techniques Authors:SHAIK SHAHUL, M. HYMAVATHI, SYED ABDUL HAQ |
11901-11904 |
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IJSETR 2057 | Analyzing the Scientific Data using Hive (Hadoop) Authors:CH. SAI SARANYA, T. SUNITHA |
11905-11911 |
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IJSETR 2058 | A Novel Architecture of Travel Package Recommendation Authors:CHEKURI AMULYA, E. SAMBASIVA RAO |
11912-11915 |
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IJSETR 2059 | Implementation of Carry Select Adder with Area-Delay-Power and Efficiency Authors:T. KANAKA DURGA, CH. NAGARAJU |
11916-11920 |
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IJSETR 2060 | Implementation of Data Encoding Techniques Reducing Network On Chip Energy Consumption Authors:T.SWAPNA, R. HARI PRASAD |
11921-11925 |
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IJSETR 2061 | FPGA Implementation of Advanced Traffic Light Controller Authors:P. SWETHA HARITHA, M.S.MANOHAR |
11926-11930 |
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IJSETR 2062 | Implementation and Design of Low Power, High Speed Full Subtractor using GDI Technique Authors:T. VINOD, M.S.MANOHAR |
11931-11936 |
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IJSETR 2063 | High Performance of Fast Radix-10 Parallel Multiplication using Redundant BCD Codes Authors:J. VIJAYALAKSHMI, K. N. V. SATYANARAYANA |
11937-11941 |
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IJSETR 2064 | Design and Implementation High Speed Vedic Multiplier Authors:MARISETTY VEERA MAHESH BABU, K. VIJAYA PRASAD |
11942-11946 |
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IJSETR 2065 | Design and Implementation of Low Power Combinational and Sequential Circuits using Reversible Logic Authors:P. JAYA LAKSHMI, K. VIJAYA PRASAD |
11947-11950 |
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