Background Subtraction Algorithm for Object Recognition Implementation on FPGA

Authors:R. RAJA SEKHAR, B. SRINIVAS

9316-9321

Implementation of Secure Digital Video Watermarking using Multiscale Decomposition and Singular Value Decompositions

Authors:P.RAJU, G.MADHAVI

9322-9325

High Performance Comparator and Adder using Parallel Prefix Tree

Authors:B. ROOPAMANJARY, K. SIVANAGI REDDY, K. DEEPIKA

9326-9331

FPGA Implementation of Convolutional Encoder and Viterbi Decoder using VHDL

Authors:M. RESHMA REDDY, P. TIRUMALA RAO

9332-9338

Preserving User Data against Untrusted Servers in Public Clouds

Authors:LALAM VENKATA SURYANARAYANA, R.CHENDRA SEKHAR

9339-9346

Parametric Studies on Stress Intensity Factors in a Fillet Welded Cruciform Joint

Authors:SRINIVASA REDDY VEMPATI, DR.K.BRAHMARAJU, DR.K.VENKATA SUBBAIAH

9347-9352

Performance Evaluation of FIR Filter with High Speed Multiplier and Low Memory Adder

Authors:R.SANDHYA, D.KRISHNA NAIK

9353-9358

An Efficient Power Generation System by using Advanced Multilevel Inverters

Authors:R.V. LAKSHMI PRASANNA, V. PRAVEEN

9359-9366

MAC Authentication for Compressed Image using Diffie-Hellman Key Exchange Algorithm

Authors:S. KIRAN, B. LAKSHMI NARAYANA REDDY, N. SUBRAMANYAN

9367-9370

Cryptographic Steganography in Images

Authors:KANUSU SRINIVASA RAO, RATNAKUMARI

9371-9374