Implementation and Analysis of Multiplier using High Speed and Area Efficient Carry Select Adders

Authors:K. JULEKHA, V. CHINNA OBULESU

8729-8733

Low Power Concept for Content Addressable Memory (CAM) Chip Design

Authors:B.SATISHCHANDRA, SHAHIDA BEGUM MOHAMMAD

8734-8738

An Efficient Avoidance of On-Chip Codeword Generation to Cope with Crosstalk

Authors:CH.VENKATRAMAIAH, NAGISETTY SUBRAHMANYAM, G. NAGESWARAONAGISETTY SUBRAHMANYAM, G. NAGESWARAO, CH.VENKATRAMAIAH

8739-8745

AMES-Cloud: Design a New Structure for Streaming High Quality and Efficient Social Video Sharing in the Clouds

Authors:NARGANI GANAPATHI, YUVARAJU CHINNAM

8746-8752

Optimal and Scalable Performance in Social Wireless Network

Authors:ADABALA S G R SRINIVAS, YUVARAJU CHINNAM

8753-8757

An Efficient SNR Estimation Scheme for Secure Communication over Fading Channel

Authors:KANDREGULA HARIBABU, B.L.PRAKASH

8758-8761

Implementation of Carry Select Adder with Low Power and Area Efficient Characteristics

Authors:G. KUMARI KANAKA RADHAMANI, BIGHNESWAR PANDA, P. ADITYA

8762-8765

Analog PLL Implementation on 180nm Technology

Authors:UDAY KUMAR ANDHUGULA, B. SWAPNA

8766-8770

Design and Implementation of Automatic Airborne Control Module

Authors:P. VISHNU VARDHAN REDDY, D. MASTAN PASHA, T. LALITH KUMAR

8771-8773

Design of Complementary Pass Transistor Logic Based Modified Booth Encoder Multiplier

Authors:PALLAPU SANTHOSH

8774-8777