Implementation of Low Power and High Speed Parallel Prefix Adders using Verilog

Authors:KOTUPALLI V NARAYANA, M.SUMALATHA

8064-8070

Security Constrained Economic Dispatch Solution with Genetic Approach

Authors:SHEFI SYED, M.PRASAD

8071-8075

Web Search for Personalized Privacy Protection on Confidential Data

Authors:B. RAMA GANESH

8076-8080

A Link-Based Cluster Ensemble Approach for Categorical Data Clustering

Authors:B. PRADEEP KUMAR REDDY, P.VEERESH

8081-8089

Realization of Reduced Complexity MDC FFT Processor for MIMO-OFDM Systems

Authors:R.RAMA MOHAN, N.SURESH BABU

8090-8093

An SOC Implementation of High Speed Switch Architecture

Authors:BANDELA SESHAGIRI, S.SUMAN

8094-8100

An Optimized Power and Area Implementation of On-Chip Network Coarse-Grained Processor

Authors:SHAIK SHAHEDA, B.RAGHAVAIAH

8101-8104

A New Approach to Implement a Low Area and High Speed EDDR Architecture

Authors:CHAVALA SIVADANARAO, B. RAGHAVAIAH

8105-8110

Low Power and Area Efficient Carry Select Adder

Authors:D.DHARMAJA, KUPPAM N CHANDRA SEKHAR, R. MALLIKARJUNA REDDY

8111-8115

Study on Voltage Unbalance Improvement using SFCL in Power Feed Network with Electric Railway System

Authors:NAGALAKSHMI, A.BHASKAR

8116-8120