Submission Open for 2024 |
Last Date of Submission : |
20th, March-2024 |
Acceptance Notification : |
After the Peer Review |
Last Date of Publication : |
30th, March-2024 |
Volume13 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
S.NO | TITLE | PAGE NO | DOWNLOAD | |
IJSETR 951 | Design of Novel Clocked Double Edge Triggered Flip Flop Authors:L.AVANTHI, PRASHANT.PISE |
5401-5404 |
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IJSETR 952 | An Enhanced Ambulance Rescue and Patient Observation System Using Green Wave Technology Authors:V. KEERTHY, V. PRATHYUSHA |
5405-5409 |
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IJSETR 953 | Deadlock Avoidance by Least Stalling method for AXI On-Chip Bus Authors:P.L.SUSMITHA, B.S.PRIYANKA KUMARI, DR. M.GURUNADHA BABU |
5410-5414 |
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IJSETR 954 | Secured Data Transmission using RC4 Algorithm: Encrypting and Decrypting Double Byte Data Authors:SAIPRIYA SAMALA, P.NAVITHA, DR. M.GURUNADHA BABU |
5415-5418 |
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IJSETR 955 | Implementation of Fast Nearest Neighbor Search in Documents using Key Words Authors:MOHD RAQUEEBUDDIN SADDAM, K.DEEPIKA |
5419-5423 |
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IJSETR 956 | Improve the Performance of LC Resonant Clock Distribution Networks Based on Low-Swing Differential Conditional Capturing Flip-Flop Authors:G.DIVYA PRANEETHA, S M SHAMSHEER DAULA |
5424-5429 |
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IJSETR 957 | Implementation of Multistandard Transform for High-Throughput Core Supporting MPEG/H.264/VC-1 Based on CSDA Authors:K.CHINMAYI, M. MADHUSUDHAN REDDY |
5430-5437 |
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IJSETR 958 | Including the Promiscuous mode in the design of MAC controller based on AXI bus and Verification with System Verilog Authors:G. VEMAN, A. SATHEESH |
5438-5445 |
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IJSETR 959 | Damping of Power System Disturbances using UPFC Based on Fuzzy Logic Authors:P. ARULPRAKASH, K.MANICHOZHAN |
5446-5451 |
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IJSETR 960 | Evaluation of Proxy-Based Web Service Adaptation System for Mobile Device Authors:SHWE THINZAR AUNG, DR. AUNG WIN |
5452-5455 |
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