VLSI Realization of Efficient ASIP Architecture for High Performance Applications

Authors:MUVVA SREENIVASA RAO

5270-5275

VLSI Implementation of Error Correcting Codes using Reversible Gates

Authors:V. ANUSHA DEVI, H. RAGHUNATHA RAO

5276-5281

Closed Loop Control of Hybrid Boosting Converter for Photovoltaic Applications

Authors:POTNURU BHARGAV, K. SAI SARITA

5282-5290

Design of Unified Power Quality Conditioner using Fuzzy Logic Controller to Improve Power Quality

Authors:VELAGALA L S S PHANI REDDY, V. NAGARAJU NAYAK

5291-5298

Providing Fine-Grained Similarity for Mining Query Facets through QDMiner

Authors:FARHA NAZNEEN, AYESHA UMAIMA

5299-5301

Joint Super Resolution and Deblocking for a Highly Compressed Image

Authors:S. RAMYAVANI, N. NAGENDRA PRASAD

5302-5309

A Normal I/O Order Radix-2 FFT Architecture to Process Two Data Streams

Authors:M. NIKITHA, DR. G. HEMA LATHA

5310-5313

Gabor Barcode Generation for Medical Images

Authors:C. SULOCHANA DEVI, A. FAROOQ HUSSAIN

5314-5318

An Efficient Error Correction Technique for Parallel FFTs

Authors:M. THARANI

5319-5323

Implementation of Redundant Binary High Speed Multipliers with Efficient Partial Product Generator

Authors:J. VAMSHI PRIYA, SYED ZAHIRUDDIN

5324-5328