Submission Open for 2024 |
Last Date of Submission : |
20th, March-2024 |
Acceptance Notification : |
After the Peer Review |
Last Date of Publication : |
30th, March-2024 |
Volume13 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
S.NO | TITLE | PAGE NO | DOWNLOAD | |
IJSETR 2140 | Securing the Data using Both Cryptography and Steganography Algorithm Implementation on FPGA Authors:L. MONICA, ALI BAIG MOHAMMED |
12385-12391 |
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IJSETR 2141 | Design and Implementation of ALU Circuit using Modified GDI Techniques Authors:B. N. SAI LAVANYA, PABBISETTI SRILAKSHMI |
12392-12395 |
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IJSETR 2142 | Design and Implementation of 1-Bit Hybrid Full Adder Design Using GDI Techniques Authors:GADHAMSETTY V SWATHI, SRIPATHI SIVA PRASAD |
12396-12401 |
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IJSETR 2143 | FPGA Implementation of Impulse Noise Removal by using New MDBUT Filter Authors:KONDRU MANIKUMAR, S. SARATHCHANDRA |
12402-12406 |
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IJSETR 2144 | Design and Simulation of Low Power Inverter Based Differential Amplifier Authors:K. SHOBHA RANI, C. SRINIVASA MURTHY |
12407-12411 |
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IJSETR 2145 | Design of a Signal Feed Back Through Pulse Triggered Flip-Flop Authors:PATIBANDLA SOWMYA, C. SRINIVASA MURTHY |
12412-12414 |
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IJSETR 2146 | Design and Implementation of Vedic Multiplier using Double Gate MOSFET Authors:BOBBILI SUMA, T. RAMBABU |
12415-12418 |
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IJSETR 2147 | Design and Implementation of 12T SRAM by using DTCMOS Technique for Reducing Static Power Dissipation Authors:YERRAMSETTI NAGARANI, A. RAJESH NAIDU |
12419-12422 |
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IJSETR 2148 | Fully Reused VLSI Architecture for FM0 and Manchester Encoding Techniques with Clock Gating Authors:P. BHAGYASRI, T. RAMBABU |
12423-12427 |
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IJSETR 2149 | Design and Implementation of Ring Oscillator Circuit using 22nm Technology Authors:S. KUSUMA, PRAVEEN KUMAR |
12428-12432 |
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